Significantly improving sub-90 nm CMOSFET performances with notch-gate enhanced high tensile-stress contact etch stop layer

Article history: Received 24 January 2008 Received in revised form 13 August 2008 Available online 1 October 2008 0026-2714/$ see front matter 2008 Elsevier Ltd. A doi:10.1016/j.microrel.2008.08.002 * Corresponding author. Tel.: +886 6 2080398; fax: E-mail addresses: [email protected] edu.tw (Y.-K. Fang). This paper reports to improve performances of sub-90 nm CMOSFETs with a notch-gate structure enhanced high tensile-stress contact etch stop layer (CESL). Compared to the conventional vertical-gate CMOSFET with an additional offset spacer, the developed structure has the notch-gate as self-aligned offset spacer and lower parasitic capacitance. Beside, the notch-gate shrinks the distance of the CESL to the channel, thus enhances the channel carrier mobility more efficiently. Consequently, an n-MOSFET with this notch-gate structure showed an extra 7% ION enhancement. For p-MOSFETs, even a tensile-stress is not preferable, however, with the structure, an extra 3% ION enhancement was still achieved due to the better channel profile by halo implantation through notch-gate structure. 2008 Elsevier Ltd. All rights reserved.